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19-3466; Rev 2; 2/08
KIT ATION EVALU LE B AVAILA
TMDS Digital Video Equalizer for DVI/HDMI Cables
General Description
The MAX3815 cable equalizer automatically provides compensation for DVITM, HDMITM, DFP, PanelLink(R), and ADC cables. It extends the usable cable distance up to 36 meters. The MAX3815 is designed to equalize signals encoded in the transition-minimized differential signaling (TMDS(R)) format. The MAX3815 features four CML-differential inputs and outputs (three data and one clock). It provides a lossof-signal (LOS) output that indicates loss-of-clock signal. The outputs include a disable function or the equalizer can be powered down to conserve power. For direct chip-to-chip communication, the output drivers can be switched to one-half the DVI output specification to conserve power and reduce EMI. Equalization can be automatic or set to manual control for specific in-cable applications. The MAX3815 is available in a 7mm x 7mm, 48-pin TQFP-EP package and operates over a 0C to +70C temperature range.
Features
Extends TMDS Cable Reach to Projectors or Monitors Using DVI, DFP, PanelLink, ADC, or HDMI Interfaces Extends TMDS Interface Length as Follows: 0 to 50 Meters Over DVI-Cable, 24 AWG STP (Shielded-Twisted Pair) 0 to 36 Meters Over DVI-Cable, 28 AWG STP 0 to 30 Meters Over DVI-Cable, 30 AWG STP Compatible with DTV Resolutions 480i, 480p, 720p, 1080i, and 1080p Compatible with Computer Resolutions VGA, SVGA, XGA, SXGA, UXGA Fully Automatic Equalization Up to 40dB at 825MHz (1.65Gbps), No System Control Required 3.3V Power Supply Power Dissipation of 0.6W (typ) 7mm x 7mm 48-Pin TQFP Lead-Free Package
MAX3815
Applications
Front-Projector DVI/HDMI Inputs High-Definition Televisions and Displays DVI-D/HDMI Cable-Extender Modules and Active Cable Assemblies LCD Computer Monitors
Pin Configuration appears at end of data sheet.
MAX3815CCM MAX3815CCM+ PART
Ordering Information
TEMP RANGE 0C to +70C 0C to +70C PINPACKAGE 48 TQFP-EP* 48 TQFP-EP* PKG CODE C48E-8 C48E-8
+Denotes lead-free package. *EP = Exposed pad.
Typical Application Circuits
VIDEO PROJECTOR
DVI-D INPUT
MAX3815
EQUALIZER
TMDS DESERIALIZER
DVI-D CABLE UP TO 36m OR 120ft (28AWG STP)
Typical Application Circuits continued at end of data sheet. DVI is a trademark of Digital Display Working Group. HDMI is a trademark of HDMI Licensing, LLC. PanelLink and TMDS are registered trademarks of Silicon Image, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
SELECT
LAPTOP
VGA INPUT
RGB/HV ADC/SYNC
IMAGE SCALER AND PROCESSOR
PANEL INTERFACE TIMING AND DRIVERS
LCD, DLP, OR LCOS
TMDS Digital Video Equalizer for DVI/HDMI Cables MAX3815
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VCC ..............................................-0.5V to +4.0V Voltage at All I/O Pins.................................-0.5V to (VCC + 0.7V) Voltage between any CML I/O Complementary Pair ..........3.3V Continuous Power Dissipation (TA = +70C) 48-Pin TQFP-EP (derate 36.2mW/C above +70C) ..2896mW Operating Junction Temperature Range ...........-55C to +150C Storage Temperature Range .............................-55C to +150C Die Attach Temperature...................................................+400C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0C to +70C. Typical Values are at VCC = +3.3V, external terminations = 50 1%, TMDS rate = 250Mbps to 1.65Gbps, TA = +25C, unless otherwise noted.)
PARAMETER Power-Supply Current Supply-Noise Tolerance EQUALIZER PERFORMANCE Residual Output Jitter (Cables Only) 0.25Gbps to 1.65Gbps (Notes 1, 2, and 3) CID Tolerance CONTROL AND STATUS CLKLOS Assert Level CML INPUTS (CABLE SIDE) Differential Input Voltage Swing Common-Mode Input Voltage Input Resistance CML OUTPUTS (ASIC SIDE) Differential Output-Voltage Swing Output-Voltage High Output-Voltage Low Output Voltage During Power-Down VOD 50 load, each side to VCC OUTLEVEL = HIGH OUTLEVEL = LOW 800 350 VCC 600 VCC 10 1000 500 VCC VCC 400 VCC +10 1200 650 mVP-P mV mV mV VID VCM RIN Single-ended At cable input 800 VCC 0.4 45 50 1000 1400 VCC + 0.1 55 mVP-P V Differential peak-to-peak at EQ input with 165MHz clock 50 mVP-P 1dB skin-effect loss at 825MHz 24dB skin-effect loss at 825MHz 40dB skin-effect loss at 825MHz 20 0.2 0.2 0.2 Bits UI SYMBOL ICC CONDITIONS PWRDWN = HIGH PWRDWN = LOW DC to 500kHz MIN TYP 165 10 200 MAX 230 UNITS mA mVP-P
Single-ended, OUTLEVEL = HIGH Single-ended, OUTLEVEL = HIGH Single-ended, PWRDWN = LOW
2
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TMDS Digital Video Equalizer for DVI/HDMI Cables
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = 0C to +70C. Typical Values are at VCC = +3.3V, external terminations = 50 1%, TMDS rate = 250Mbps to 1.65Gbps, TA = +25C, unless otherwise noted.)
PARAMETER Common-Mode Output Voltage Rise/Fall Time (Note 1) LVTTL CONTROL AND STATUS INTERFACE LVTTL Input High Voltage LVTTL Input Low Voltage LVTTL Input High Current LVTTL Input Low Current Open-Collector Output High Open-Collector Output Low Open-Collector Output Sink VIH VIL VIH(MIN) < VIN < VCC GND < VIN < VIL(MAX) RLOAD 10k to VCC RLOAD 2k to VCC 2.4 0.4 5 2.0 0.8 -50 -100 V V A A V V mA SYMBOL CONDITIONS 50 load, each side to VCC, OUTLEVEL = HIGH 20% to 80% 80 MIN TYP VCC 0.25 130 200 MAX UNITS V ps
MAX3815
Note 1: AC specifications are guaranteed by design and characterization. Note 2: Cable input swing is 800mV to 1400mV differential peak-to-peak. Residual output jitter is defined as peak-to-peak deterministic jitter + 14.2 times random jitter. Note 3: Test pattern is a 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros.
Typical Operating Characteristics
(Typical values are at VCC = +3.3V, TA = +25C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX3815 toc01
DIFFERENTIAL INPUT RETURN LOSS vs. FREQUENCY
MAX3815 toc02
EQUALIZER INPUT AFTER 205ft OF GORE 89 CABLE (TOP) EQUALIZER OUTPUT (BOTTOM)
MAX3815 toc03
200 190 180 SUPPLY CURRENT (mA) 170 OUTLEVEL = HIGH
0 -5 -10 -15 GAIN (dB) -20 -25 -30 -35 -40 -45 -50
DATA RATE = 1.65Gbps 40dB CABLE SKIN-EFFECT LOSS AT 825MHz
128mV/div
160 150 140 130 120 110 100 0 10 20 30 40 50 60 70 TEMPERATURE (C) OUTLEVEL = LOW
350mV/div
0
500
1000
1500
2000
2500
3000
5ns/div
FREQUENCY (MHz)
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3
TMDS Digital Video Equalizer for DVI/HDMI Cables MAX3815
Typical Operating Characteristics (continued)
(Typical values are at VCC = +3.3V, TA = +25C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, unless otherwise noted.)
EQUALIZER INPUT EYE AFTER 205ft OF GORE 89 CABLE (TOP) EQUALIZER OUTPUT (BOTTOM)
MAX3815 toc04
EQUALIZER INPUT EYE AFTER 205ft OF GORE 89 CABLE (TOP) EQUALIZER OUTPUT (BOTTOM)
MAX3815 toc05
EQUALIZER EYES AFTER 100ft MADISON DIGITAL FLAT-PANEL CABLE, 28 AWG (DATA RATE = 1.65Gbps)
MAX3815 toc06
DATA RATE = 1.65Gbps 40dB CABLE SKIN-EFFECT LOSS AT 825MHz
DATA RATE = 250Mbps 40dB CABLE SKIN-EFFECT LOSS AT 825MHz
350mV/div
300mV/div
350mV/div
152ps/div
1ns/div
200ps/div
EQUALIZER EYES AFTER 100ft MADISON DIGITAL FLAT-PANEL CABLE, 28 AWG (DATA RATE = 350Mbps)
MAX3815 toc07
EQUALIZER EYES AFTER 3ft CABLE (DATA RATE = 1.65Gbps)
MAX3815 toc08
JITTER vs. DATA RATE AFTER 205ft CABLE WITH 40dB SKIN-EFFECT LOSS AT 825MHz
GORE 89 CABLE 100 80 60 40 20 DETERMINISTIC JITTER 0 RESIDUAL JITTER = DJ + 14.2 x RJ
MAX3815 toc09
120
350mV/div
350mV/div
JITTER (psP-P)
1ns/div
200ps/div
250
450
650
850
1050 1250 1450 1650
DATA RATE (Mbps)
TOTAL JITTER vs. POWER-SUPPLY NOISE FREQUENCY (DATA RATE = 1.65Gbps)
MAX3815 toc10
DETERMINISTIC JITTER vs. CABLE LENGTH (TENSOLITE TWIN-AX 28 AWG)
MAX3815 toc11
RESIDUAL JITTER vs. SIGNAL AMPLITUDE INPUT TO CABLE (DATA RATE = 1.65Gbps)
205ft OF GORE 89 CABLE WITH 40dB SKINEFFECT LOSS AT 825MHz RESIDUAL JITTER = DJ + 14.2 X RJ
MAX3815 toc12
180 170 TOTAL JITTER (psP-P) 160 150 140 130 120 110 100 1
0.6 1.65Gbps DETERMINISTIC JITTER (UIP-P) 0.5 800Mbps 0.4 250Mbps 0.3 0.2 0.1 0 NO EQ
NOISE AMPLITUDE: 200mVP-P DATA THROUGH 100ft MADISON DIGITAL FLAT-PANEL CABLE, 28AWG
120 110 RESIDUAL JITTER (psP-P) 100 90 80 70 60
WITH MAX3815 EQ
10
100
1000
10,000 100,000
0
50
100 CABLE LENGTH (ft)
150
200
0.6
0.8
1.0
1.2
1.4
FREQUENCY (kHz)
DIFFERENTIAL AMPLITUDE (mVP-P)
4
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TMDS Digital Video Equalizer for DVI/HDMI Cables
Typical Operating Characteristics (continued)
(Typical values are at VCC = +3.3V, TA = +25C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, unless otherwise noted.)
EQCONTROL VOLTAGE (RELATIVE TO VCC) vs. CABLE LENGTH (MANUAL EQ CONTROL)
0 -0.1 EQCONTROL VOLTAGE (V) -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 0 20 40 60 80 100 CABLE LENGTH (ft) RESIDUAL JITTER AT 1.65Gbps CABLE IS TENSOLITE TWIN-AX 28 AWG WITH APPROXIMATELY 0.34dB OF LOSS PER FOOT AT 825MHz EQCONTROL VOLTAGE
MAX3815 toc13
MAX3815
EQUALIZER OUTPUT EYE AFTER 120ft OF CABLE (DATA RATE = 1.65Gbps)
MAX3815 toc14
LOSS-OF-CLOCK ASSERT THRESHOLD vs. CABLE LENGTH
DIFFERENTIAL CLOCK AMPLITUDE (mVP-P) CABLE IS TENSOLITE TWIN-AX 28 AWG 300 250 200 150 100 50 25MHz CLOCK FREQUENCY 0 0 20 40 60 80 100 120
MAX3815 toc15
200 180 160 140 120 100 80 60 40 20 RESIDUAL JITTER (psP-P)
350
CABLE IS TENSOLITE TWIN-AX 28 AWG
200mV/div
165MHz CLOCK FREQUENCY
0 120
100ps/div
CABLE LENGTH (ft)
Pin Description
PIN 1, 4, 5, 8, 9, 12, 13, 16, 38, 41, 43, 44 2 3 6 7 10 11 14 15 NAME VCC RX0_INRX0_IN+ RX1_INRX1_IN+ RX2_INRX2_IN+ RXC_IN+ RXC_INFUNCTION Supply Voltage. All pins must be connected to VCC. Negative Data Input, CML Positive Data Input, CML Negative Data Input, CML Positive Data Input, CML Negative Data Input, CML Positive Data Input, CML Positive Clock Input, CML Negative Clock Input, CML
17
Equalizer Control. This pin allows the user to control the equalization level of the MAX3815. Connect the pin to GND for automatic operation. Set the voltage to VCC / 2 for minimum equalization, or set EQCONTROL the voltage between VCC - 1V to VCC for manual equalization. See the Typical Operating Characteristics for more information. CLKLOS PWRDWN Loss-of-Clock Signal Output, LVTTL Open Collector. This pin asserts low upon loss of the input TMDS clock from the cable. Power-Down Input, LVTTL. This input allows the IC to be powered down to conserve power. Connect high for normal operation. Pull low for power-down mode.
18 19
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5
TMDS Digital Video Equalizer for DVI/HDMI Cables MAX3815
Pin Description (continued)
PIN 20, 23, 24, 25, 28, 29, 32, 33, 36, 37, 42 21 22 26 27 30 31 34 35 39 40 45-48 EP NAME FUNCTION
GND
Ground
RXC_OUTRXC_OUT+ RX2_OUT+ RX2_OUTRX1_OUT+ RX1_OUTRX0_OUT+ RX0_OUTOUTLEVEL OUTON N.C. Exposed Pad
Negative Clock Output, CML Positive Clock Output, CML Positive Data Output, CML Negative Data Output, CML Positive Data Output, CML Negative Data Output, CML Positive Data Output, CML Negative Data Output, CML Output-Level Control Input, LVTTL. This input sets the output amplitude to the standard DVI level (1000mVP-P) when high, and sets the output amplitude to 1/2 the DVI level (500mVP-P) when low. Output-Enable Control Input, LVTTL. This input enables the CML outputs when forced low and sets a differential logic zero when forced high. No Connection Ground. The exposed pad must be soldered to the circuit-board ground for proper thermal and electrical operation.
Detailed Description
The MAX3815 TMDS equalizer accepts differential CML input data at rates of 250Mbps up to 1.65Gbps (individual channel data rate). It automatically adjusts to attenuation levels of up to 40dB at 825MHz due to skin-effect losses in copper cable. It consists of four CML input buffers, a loss-of-clock signal detector, three independent adaptive equalizers, four limiting amplifiers, and four output buffers (Figure 1).
Adaptive Equalizer
The three data channels each contain an independent adaptive equalizer. Each channel analyzes the incoming signal and determines the amount of equalization to apply.
Limiting Amplifier
The limiting amplifier amplifies the signal from the adaptive equalizer and truncates the top and bottom of the waveform to provide a clean high- and low-level signal to the output drivers.
CML Input Buffers and Output Drivers
The input buffers and the output drivers are implemented using current-mode logic (CML) (see Figures 3 and 4). The output drivers are open-collector and can be turned off with the OUTON pin, or can be set to output a one-half amplitude signal (500mV P-P differential) using the OUTLEVEL pin. For details on interfacing with CML, refer to Maxim Application Note HFAN-01.0: Introduction to LVDS, PECL, and CML.
Applications Information
Typical shielded twisted pair (STP) and unshielded twisted pair (UTP) cables exhibit skin-effect losses, which attenuate the high-frequency spectrum of a TMDS signal, eventually causing data errors or even closing the signal eye altogether given a long enough cable. The MAX3815 recovers the data and opens the signal eye through compensating equalization. The basic TMDS interface is composed of four differential serial links: three links carry serial data up to 1.65Gbps each, and the fourth is a one-tenth-rate (0.1x) clock that operates up to 165MHz. TMDS, as with
Loss-of-Clock Signal Detector
The loss-of-clock signal detector indicates a loss-ofclock signal at the CLKLOS pin.
6
_______________________________________________________________________________________
TMDS Digital Video Equalizer for DVI/HDMI Cables MAX3815
TERMINATED 3.3V CML
RX2_IN+/-
INPUT BUFFER
ADAPTIVE EQ
LIMITING AMPLIFIER
DRIVER
RX2_OUT+/-
RX1_IN+/-
TERMINATED 3.3V CML
INPUT BUFFER
ADAPTIVE EQ
LIMITING AMPLIFIER
DRIVER
RX1_OUT+/-
RX0_IN+/-
TERMINATED 3.3V CML
INPUT BUFFER
ADAPTIVE EQ
LIMITING AMPLIFIER
DRIVER
RX0_OUT+/-
EQCONTROL TERMINATED 3.3V CML INPUT BUFFER LIMITING AMPLIFIER
RXC_IN+/-
DRIVER
RXC_OUT+/-
CLKLOS
CLOCK LOS DETECTOR
OUTON MAX3815 OUTLEVEL
Figure 1. Functional Diagram
analog nVGA links, must handle a variety of resolutions and screen update rates. The actual range of digital serial rates is roughly 250Mbps to 1.65Gbps. For applications requiring ultra-high resolutions (e.g., QXGA), a "double-link" TMDS interface is used and is composed of six data links plus the clock, requiring two MAX3815 ICs with the clock going to both ICs. See Figure 2. The MAX3815 can be used to extend any TMDS interface as used under the following trademarked names: DVI (digital visual interface), DFPTM (digital flat-panel), PanelLink, ADCTM (Apple display connector), and HDMI (high-definition multimedia interface).
D0 D1 D2
D0 D1 D2
MAX3815
CLK CLK
D3 D4 D5
MAX3815
D3 D4 D5
Loss-of-Clock Signal (CLKLOS) Output
Loss-of-clock signal is indicated by the CLKLOS output. A low level on CLKLOS indicates that the signal power on the RXC_IN pins has dropped below a threshold. When there is sufficient input voltage to the channel (typically greater than 100mVP-P differential), CLKLOS is high. The CLKLOS output is suitable for indicating problems with the transmission link caused by, for example, a broken cable, a defective driver, or a lost connection to the equalizer.
Figure 2. Connection Scheme for MAX3815 in Dual Link Application
ADC is a trademark of Apple Computer, Inc. DFP is a trademark of Video Electronics Standards Association (VESA).
_______________________________________________________________________________________
7
TMDS Digital Video Equalizer for DVI/HDMI Cables MAX3815
A squelching function can be created by sending the CLKLOS output through an inverter to the OUTON pin. This will squelch the CML outputs whenever the clock signal is removed. A loss-of-signal LED indicator can be incorporated into the circuit as well (see Figure 3).
VCC
10k 4.7k CLKLOS OUTON 200
Output Level Control (OUTLEVEL) Input
The OUTLEVEL pin is an LVTTL input that allows the user to select between standard output amplitude (1000mVP-P differential) or one-half output amplitude (500mVP-P differential). Forcing this pin high results in the standard output signal level, and forcing this pin low results in the reduced output signal level.
Equalizer Control (EQCONTROL) Input
The EQCONTROL pin allows the user to control the equalization in one of three ways: forcing the pin to ground sets the equalizer in automatic equalization mode, forcing the pin to VCC / 2 sets the equalizer to minimum equalization, and forcing a voltage between VCC - 1V to VCC allows manual control of the equalization level applied to the input signals. See the Typical Operating Characteristics for more information.
LOSS-OF-CLOCK LED
Figure 3. Squelch Circuit
Output On (OUTON) Input
The OUTON pin is an LVTTL input. Force the pin low to enable the outputs. Force the pin high to set a differential zero on the outputs. When disabled, the outputs will go to a differential zero, irrespective of the signal at the inputs.
Power-Down (PWRDWN) Input
The PWRDWN pin allows the part to be powered down to reduce system power consumption. Force the pin high for normal operation. Force the pin low to powerdown the IC. When powered down, the part consumes approximately 10mA.
Cable Selection
TMDS performance is heavily dependent on cable quality. Deterministic jitter (DJ) can be caused by differential-to-common-mode conversion (or vice-versa)
Interface Models
VCC
MAX3815
MAX3815
VCC
RX_OUT+ RX_OUT-
50 RX_IN+/-
Figure 4. Simplified Input Circuit Schematic
8
Figure 5. Simplified Output Circuit Schematic
_______________________________________________________________________________________
TMDS Digital Video Equalizer for DVI/HDMI Cables
TYPICAL MAX3815 CABLE REACH
60 50 CABLE LENGTH (meters) 40 30 20 10 5 32 AWG
* Input and output data channel designations are only a guide. Polarity assignments can be swapped and channel paths can be interchanged. * An uninterrupted ground plane should be positioned beneath the high-speed I/Os. * Ground-path vias should be placed close to the IC and the input/output interfaces to allow a return current path to the IC and the DVI cable. * Maintain 100 differential transmission line impedance into and out of the MAX3815. * Use good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk.
MAX3815
5 381 E AX ANG ps = M TH R 65Gb REA NG 1. D A LE TO DE ABLE S UP A SH LE C ATE IR AB US LL DV TA A
AT NGTH WITHOUT EQ LIMIT OF CABLE LE
1.65Gbps
TYPICAL DVI WIRE GAUGE RANGE 30 AWG 28 26 AWG AWG DVI WIRE GAUGE 24 AWG 22 AWG
Exposed-Pad Package
The exposed pad on the 48-pin TQFP-EP provides a very low thermal resistance path for heat removal from the IC. The pad is also electrical ground on the MAX3815 and must be soldered to the circuit board ground for proper thermal and electrical performance. Refer to Maxim Application Note HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages for additional information.
Figure 6. Cable Reach
within a twisted pair (STP or UTP), usually a result of cable twist or dielectric imbalance. Refer to Application Note HFAN-04.5.4: `Jitter Happens' when a Twisted Pair is Unbalanced for more information.
Chip Information
PROCESS: SiGe BiPOLAR
Layout Considerations
The data and clock inputs are the most critical paths for the MAX3815 and great care should be taken to minimize discontinuities on these transmission lines between the connector and the IC. Here are some suggestions for maximizing the performance of the MAX3815: * The data and clock inputs should be wired directly between the cable connector and IC without stubs.
Package Information
(For the latest package outline information, go to www.maxim-ic.com/packages.) PACKAGE TYPE 48 TQFP DOCUMENT NO. 21-0065
_______________________________________________________________________________________
9
TMDS Digital Video Equalizer for DVI/HDMI Cables MAX3815
Typical Application Circuits (continued)
DVI-D OR HDMI EXTENDER BOX UP TO 36m OF DVI-D OR HDMI CABLE (28 AWG) STANDARD LENGTH DVI-D OR HDMI CABLE HDTV
MAX3816
DDC EXTENDER
MAX3815
EQUALIZER
VIDEO SOURCE
DIGITAL BROADCAST DIGITAL CABLE DIGITAL SATELLITE DVD Blu-ray DiscTM
Blu-ray Disc IS A TRADEMARK OF Blu-ray DISC ASSOCIATION.
Pin Configuration
OUTON TOP VIEW GND N.C. N.C. N.C. N.C. VCC VCC VCC OUTLEVEL GND 36 GND 35 RX0_OUT34 RX0_OUT+ 33 GND 32 GND 31 RX1_OUT30 RX1_OUT+ 29 GND 28 GND 27 RX2_OUT26 RX2_OUT+ 25 GND 13 14 15 16 17 18 19 20 21 22 23 24 GND RXC_OUTRXC_OUT+ GND EQCONTROL CLKLOS PWRDWN RXC_IN+ RXC_INGND VCC VCC VCC
48 47 46 45 44 43 42 41 40 39 38 37 VCC 1 RX0_IN- 2 RX0_IN+ 3 VCC 4 VCC 5 RX1_IN- 6 RX1_IN+ 7 VCC 8 VCC 9 RX2_IN- 10 RX2_IN+ 11 VCC 12
MAX3815
48 TQFP-EP
10
______________________________________________________________________________________
TMDS Digital Video Equalizer for DVI/HDMI Cables
Revision History
REVISION NUMBER 0 1 2 REVISION DATE 10/04 8/05 2/08 Initial release. Removed future status from the lead-free package in the Ordering Information table. Removed reference to the schematic and board layers in the Layout Considerations section. DESCRIPTION PAGES CHANGED -- 1 9
MAX3815
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
(c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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